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| CY62138FV30 MoBL(R) 2-Mbit (256K x 8) Static RAM Features * * * * Very high speed: 45 ns Wide voltage range: 2.20V-3.60V Pin compatible with CY62138CV25/30/33 Ultra low standby power -- Typical standby current: 1 A -- Maximum standby current: 5 A * Ultra low active power * * * * -- Typical active current: 1.6 mA @ f = 1 MHz Easy memory expansion with CE1, CE2, and OE features Automatic power down when deselected CMOS for optimum speed and power Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin SOIC, 32-pin TSOP I and 32-pin STSOP packages Functional Description [1] The CY62138FV30 is a high performance CMOS static RAM organized as 256K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Place the device into standby mode reducing power consumption when deselected (CE1 HIGH or CE2 LOW). To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW and CE2 HIGH and WE LOW). Logic Block Diagram CE1 CE2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 WE OE DATA IN DRIVERS IO0 IO1 ROW DECODER 256K x 8 ARRAY SENSE AMPS IO2 IO3 IO4 IO5 IO6 COLUMN DECODER POWER DOWN IO7 Note 1. For best practice recommendations, refer to the Cypress application note "System Design Guidelines" at http://www.cypress.com. Cypress Semiconductor Corporation Document #: 001-08029 Rev. *E * 198 Champion Court A15 A16 A17 A12 A13 A14 * San Jose, CA 95134-1709 * 408-943-2600 Revised March 26, 2007 [+] Feedback CY62138FV30 MoBL(R) Pin Configuration [2] 36-Ball VFBGA Top View A3 A4 A5 32-Pin SOIC/TSOP II Top View A6 A7 A8 IO 0 IO 1 VCC VSS A B C D E F G H A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A0 IO 4 IO 5 VSS VCC IO 6 IO 7 A9 A1 A2 CE2 WE NC NC OE A10 CE1 A11 A17 A16 A12 A15 A13 IO 2 IO 3 A14 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 IO7 IO6 IO5 IO4 IO3 A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TSOP I Top View (not to scale) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A0 A1 A2 A3 A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 25 26 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 STSOP Top View (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OE A10 CE1 IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A0 A1 A2 A3 Product Portfolio Power Dissipation Product Min CY62138FV30LL 2.2 VCC Range (V) Typ [3] 3.0 Max 3.6 45 Speed (ns) Operating ICC (mA) f = 1 MHz Typ [3] 1.6 Max 2.5 f = fmax Typ [3] 13 Max 18 Standby ISB2 (A) Typ [3] 1 Max 5 Note 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C. Document #: 001-08029 Rev. *E Page 2 of 13 [+] Feedback CY62138FV30 MoBL(R) Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied............................................... 55C to +125C Supply Voltage to Ground Potential ........................................................... -0.3V to 3.9V DC Voltage Applied to Outputs in High-Z State [4, 5] .......................................... -0.3V to 3.9V DC Input Voltage [4, 5] .......................................-0.3V to 3.9V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA Product Range Ambient Temperature VCC [6] CY62138FV30LL Industrial -40C to +85C 2.2V to 3.6V Electrical Characteristics (Over the Operating Range) Parameter VOH VOL VIH VIL Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Test Conditions IOH = -0.1 mA IOH = -1.0 mA, VCC > 2.70V IOL = 0.1 mA IOL = 2.1 mA, VCC > 2.70V VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V VCC = 2.2V to 2.7V For BGA package VCC= 2.7V to 3.6V VCC = 2.2V to 3.6V For other packages IIX IOZ ICC Input Leakage Current Output Leakage Current GND < VI < VCC GND < VO < VCC, output disabled f = 1 MHz ISB1 Automatic CE Power Down Current CMOS Inputs VCC = VCCmax IOUT = 0 mA CMOS levels 1.8 2.2 -0.3 -0.3 -0.3 -1 -1 13 1.6 1 45 ns Min 2.0 2.4 0.4 0.4 VCC + 0.3V VCC + 0.3V 0.6 0.8 0.6 +1 +1 18 2.5 5 A Typ [3] Max Unit V V V V V V V V V A A mA VCC Operating Supply Current f = fmax = 1/tRC CE1 > VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V, VIN < 0.2V), f = fmax (address and data only), f = 0 (OE, and WE), VCC = 3.60V ISB2 [7] Automatic CE Power Down Current CMOS Inputs CE1 > VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V 1 5 A Capacitance (For all packages) [8] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ.) Max 10 10 Unit pF pF Notes 4. VIL(min) = -2.0V for pulse durations less than 20 ns. 5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns. 6. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 7. Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 8. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-08029 Rev. *E Page 3 of 13 [+] Feedback CY62138FV30 MoBL(R) Thermal Resistance [8] Parameter JA JC Description Test Conditions SOIC 44.53 24.05 VFBGA 38.49 17.66 TSOP II 44.16 11.97 STSOP 59.72 15.38 TSOP I 50.19 14.59 Unit C/W C/W Thermal Resistance Still air, soldered on a 3 x 4.5 (Junction to Ambient) inch, two layer printed circuit Thermal Resistance board (Junction to Case) AC Test Loads and Waveforms R1 VCC 30 pF INCLUDING JIG AND SCOPE R2 GND Rise Time = 1 V/ns 10% VCC OUTPUT ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT OUTPUT RTH V Parameters R1 R2 RTH VTH 2.5V (2.2V to 2.7V) 16667 15385 8000 1.20 3.0V (2.7V to 3.6V) 1103 1554 645 1.75 Unit V Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR [7] Description VCC for Data Retention Data Retention Current Conditions VCC = 1.5V, CE1 > VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Min 1.5 Typ [3] 1 Max 4 Unit V A tCDR [8] tR [9] Chip Deselect to Data Retention Time Operation Recovery Time 0 tRC ns ns Data Retention Waveform [10] DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5V VCC(min) tR CE Notes: 9. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 10. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document #: 001-08029 Rev. *E Page 4 of 13 [+] Feedback CY62138FV30 MoBL(R) Switching Characteristics (Over the Operating Range) [11] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE [14] Description 45 ns Min Max Unit Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low-Z [12] OE HIGH to High-Z [12,13] [12] 45 45 10 45 22 5 18 10 18 0 45 [12, 13] ns ns ns ns ns ns ns ns ns ns ns CE1 LOW and CE2 HIGH to Low Z CE1 HIGH or CE2 LOW to High-Z CE1 LOW and CE2 HIGH to Power Up CE1 HIGH or CE2 LOW to Power Down Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z [12, 13] 45 35 35 0 0 35 25 0 18 10 ns ns ns ns ns ns ns ns ns ns WE HIGH to Low-Z [12] Notes 11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the ""AC Test Loads and Waveforms" on page 4" . 12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 13. tHZOE, tHZCE, and tHZWE transitions are measured when the output enters a high impedance state. 14. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write. Document #: 001-08029 Rev. *E Page 5 of 13 [+] Feedback CY62138FV30 MoBL(R) Switching Waveforms Read Cycle 1 (Address transition controlled) [15, 16] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE controlled) [10, 16, 17] ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tPU 50% tLZCE DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE ICC ISB Write Cycle No. 1 (WE controlled) [10, 14, 18, 19] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA IO NOTE 20 tHZOE Notes: 15. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 16. WE is HIGH for read cycle. 17. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. 18. Data IO is high impedance if OE = VIH. 19. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 20. During this period, the IOs are in output state. Do not apply input signals. tHD DATA VALID Document #: 001-08029 Rev. *E Page 6 of 13 [+] Feedback CY62138FV30 MoBL(R) Switching Waveforms (continued) Write Cycle No. 2 (CE1 or CE2 controlled) [10, 14, 18, 19] tWC ADDRESS tSCE tSA tAW tPWE WE tSD DATA IO DATA VALID tHD tHA CE Write Cycle No. 3 (WE controlled, OE LOW) [10, 19] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA IO NOTE 20 tHZWE DATA VALID tPWE tHA tHD tLZWE Truth Table CE1 H X L L L CE2 X L H H H WE X X H H L OE X X L H X High-Z High-Z Data Out High-Z Data in Inputs/Outputs Mode Deselect/Power Down Deselect/Power Down Read Output Disabled Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Document #: 001-08029 Rev. *E Page 7 of 13 [+] Feedback CY62138FV30 MoBL(R) Ordering Information Speed (ns) 45 Ordering Code CY62138FV30LL-45BVXI CY62138FV30LL-45ZSXI CY62138FV30LL-45ZAXI CY62138FV30LL-45ZXI CY62138FV30LL-45SXI Package Diagram 51-85149 51-85095 51-85094 51-85056 51-85081 Package Type 36-ball VFBGA (Pb-free) 32-pin TSOP II (Pb-free) 32-pin STSOP (Pb-free) 32-pin TSOP I (Pb-free) 32-pin SOIC (Pb-free) Operating Range Industrial Package Diagrams Figure 1. 36-ball VFBGA (6 x 8 x 1 mm), 51-85149 TOP VIEW BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(36X) 1 2 3 4 5 6 6 5 4 3 2 1 A B C 8.000.10 8.000.10 0.75 5.25 A B C D E 2.625 D E F G H F G H A B 6.000.10 A 1.875 0.75 3.75 B 6.000.10 0.55 MAX. 0.25 C 0.15(4X) 0.210.05 0.10 C 1.00 MAX SEATING PLANE 0.26 MAX. C 51-85149-*C Document #: 001-08029 Rev. *E Page 8 of 13 [+] Feedback CY62138FV30 MoBL(R) Package Diagrams (continued) Figure 2. 32-pin TSOP II, 51-85095 51-85095-** Document #: 001-08029 Rev. *E Page 9 of 13 [+] Feedback CY62138FV30 MoBL(R) Package Diagrams (continued) Figure 3. 32-pin (450 Mil) Molded SOIC, 51-85081 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 17 32 0.793[20.142] 0.817[20.751] 0.006[0.152] 0.012[0.304] 0.101[2.565] 0.111[2.819] 0.118[2.997] MAX. 0.004[0.102] 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990] 0.050[1.270] BSC. 0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] SEATING PLANE 51-85081-*B Document #: 001-08029 Rev. *E Page 10 of 13 [+] Feedback CY62138FV30 MoBL(R) Package Diagrams (continued) Figure 4. 32-pin TSOP I (8 x 20 mm), 51-85056 51-85056-*D Document #: 001-08029 Rev. *E Page 11 of 13 [+] Feedback CY62138FV30 MoBL(R) Package Diagrams (continued) Figure 5. 32-pin STSOP (8 x 13.4 mm), 51-85094 51-85094-*D MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-08029 Rev. *E Page 12 of 13 (c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62138FV30 MoBL(R) Document History Page Document Title: CY62138FV30 MoBL(R), 2-Mbit (256K x 8) Static RAM Document Number: 001-08029 REV. ** *A *B ECN NO. 463660 467351 566724 Issue Date See ECN See ECN See ECN Orig. of Change NXR NXR NXR New data sheet Added 32-pin TSOP II package, 32 pin TSOP I and 32 pin STSOP packages Changed ball A3 from NC to CE2 in 36-ball FBGA pin out Converted from Preliminary to Final Corrected typo in 32 pin TSOP II pin configuration diagram on page #2 (changed pin 24 from CE1to OE and pin 22 from CE to CE1) Changed the ICC(max) value from 2.25 mA to 2.5 mA for test condition f=1 MHz Changed the ISB2(typ) value from 0.5 A to 1 A Changed the ISB2(max) value from 2.5 A to 5 A Changed the ICCDR(typ) value from 0.5 A to 1 A and ICCDR(max) value from 2.5 A to 4 A Added 32-pin SOIC package Updated VIL spec for SOIC, TSOP-II, TSOP-I, and STSOP packages on Electrical characteristics table Corrected typo in the Ordering Information table Added footnote #7 related to ISB2 and ICCDR Description of Change *C 797956 See ECN VKN *D *E 809101 940341 See ECN See ECN VKN VKN Document #: 001-08029 Rev. *E Page 13 of 13 [+] Feedback |
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